This invention relates generally to computer systems. In particular this invention relates to microcomputer systems including one or more peripheral input/output devices such as printers, modems, disc controllers, keyboards, etc. One method of servicing such requests is to program the central processor to periodically poll the various peripherals to determine whether any require service by the central processor. Alternatively, and of particular concern to the present invention are systems which utilize an interrupt signal provided by the peripheral device to request servicing by a central source such as a microprocessor, thereby avoiding the regular polling of the devices by the central processor.
In such interrupt driven systems, the peripheral devices execute certain tasks independently of the central source or microprocessor, but require communication with the microprocessor at irregular, random and therefore asynchronous intervals. In such systems the particular peripheral device or subsystem generates an interrupt signal which is passed on to the central processing unit or microprocessor via a dedicated interrupt line or channel to request that the central processing unit interrupt its processing and communicate with the peripheral device or subsystem. Upon detecting an active interrupt request the central processor transfers control to service the particular request.
In typical interrupt driven systems, a processor services many peripheral devices over a single input/output channel which can only be utilized by one peripheral at a time. Consequently, the operator will want to assign priorities to the various peripheral devices to discriminate between concurrent interrupt requests to service the most urgent before the others. Conventional systems have dealt with the problem of multiple interrupt sources by providing an interface circuit between the central processor and the peripherals to centrally sort, prioritize and control the interrupt sequencing. One such circuit is the 8259 series programmable interrupt controller manufactured by the Intel Corporation and described in the publication "Microprocessor and Peripheral Handbook": Vol. 1, pp. 2-271 through 2-314 (Intel Corporation 1987). This manual is incorporated herein by reference.
The typical interrupt controller handles interrupt requests from eight or more peripherals or subsystems. Each interrupt source is provided an interrupt service routine at a specified vectoral address for servicing the interrupt request. Each interrupt source has its own interrupt request line, and programmable controllers such as the Intel 8259 allow for identification and prioritizing the various sources on system initialization. In typical operation, the interrupt controller recognizes interrupt requests and passes the highest priority request to the central processor, holding lower priority requests until the processor has completed servicing the interrupt in progress.
Of particular importance to the present invention are the conventions adopted in the industry concerning the physical parameters of interrupt signals originating in the interrupt sources and which are transmitted to the interrupt controller. Interrupt sources utilized currently generate one of two types of interrupt signals. The first is known as edge triggered and consists of a pulse signal transitioning from a logic low level voltage to a logic high level. Alternatively, some interrupt sources provide a level interrupt request signal as distinguished from an edge sensed signal transitioning from low to high. Level sensing facilitates interrupt level sharing by more than one interrupt source and is the mode of choice for fully loaded systems to permit multiple interrupt sources such as serial ports to share a single interrupt line. Because of the variance between conventions, it has become important for the interrupt controller to be able to recognize either type of interrupt signal.
To accommodate this, interrupt controllers like the 8259A from Intel Corporation have been designed to allow the user to designate upon initialization of the system which interrupt convention is to be sensed. FIG. 1 is a block diagram of the typical prior art controller such as the Intel 8259A. FIG. 2 is a schematic illustration of the simplified logic circuit of the 8259A relating to interrupt recognition. During initialization the 8259A interrupt controller in response to user designation issues one of two command words which set the controller to recognize edge sensed interrupts or disables the edge sense logic to permit interrupts to be recognized by the controller upon receipt of a level high interrupt request (FIG. 1).
While this feature has advantages over prior systems, it does not permit the user to program each of the interrupt lines independently, to provide interrupt control for a computer system wherein some interrupt sources generate edge sensed signals and others generate level interrupt signals. In situations where a system includes more interrupt sources than it has available interrupt lines to the interrupt controller, or where it is desirable to place more than one source on an interrupt line of a particular priority level, some form of level sharing is highly desirable. To share interrupt lines it is necessary to connect more than one interrupt source in parallel to an interrupt request line. Edge sensed interrupt devices typically produce the low to high transition signal by taking the output terminal connected to the interrupt request line to ground until an interrupt is desired and then release it to go high. Consequently, it is very difficult to accommodate multiple parallel sources on the same line since the output will not transition to the high level if any of the parallel sources are concurrently holding the output to ground level. Prior systems such as that disclosed in U.S. Pat. No. 4,631,670 have attempted to resolve this problem by utilizing complex and expensive additional circuitry.
In contrast, level sensed interrupt devices can easily be placed in parallel since a resistor pulls the line high when no interrupt is required and the device takes the output terminal low and holds it until serviced. The ability to provide one or more interrupt lines on an interrupt controller which are level sensed, while keeping the others edged sensed greatly facilitates the assembly of varied interrupt devices and the sharing of interrupt lines by more than one peripheral without involving complex an costly additional circuitry.